The Resource Electronic Chips & Systems Design Languages, edited by Jean Mermet, (electronic resource)

Electronic Chips & Systems Design Languages, edited by Jean Mermet, (electronic resource)

Label
Electronic Chips & Systems Design Languages
Title
Electronic Chips & Systems Design Languages
Statement of responsibility
edited by Jean Mermet
Creator
Subject
Genre
Language
eng
Summary
Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates
Cataloging source
AU@
http://library.link/vocab/creatorName
Mermet, Jean
Dewey number
004
Index
no index present
LC call number
  • QA75.5-76.95
  • TK7885-7895
Literary form
non fiction
Nature of contents
dictionaries
http://library.link/vocab/subjectName
  • Computer science
  • Computer hardware
  • Electronic data processing
  • Computer-aided design
  • Engineering
Label
Electronic Chips & Systems Design Languages, edited by Jean Mermet, (electronic resource)
Link
http://dx.doi.org/10.1007/978-1-4757-3326-6
Instantiates
Publication
Antecedent source
file reproduced from original
Color
mixed
Contents
VHDL Extensions -- 1. Library Development Using the VHDL-AMS Language -- 2. Behavioral Modeling of Complex Heterogeneous Microsystems -- 3. VHDL-AMS, a Unified Language to Describe Multi-Domain, Mixed-Signal Designs. Mechatronic Applications -- 4. Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique -- 5. SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling -- 6. Digital Circuit Design with Objective VHDL -- System Level Design -- 7. UF: Architecture and Semantics for System-Level Multiformalism Descriptions -- 8. Automatic Interface Generation among VHDL Processes in HW/SW Co-Design -- 9. System-Level Specification and Architecture Exploration: An Avionics Codesign Application -- 10. Using SDL to Model Reactive Embedded System in a Co-design Environment -- 11. A Synchronous Object-Oriented Design Flow for Embedded Applications -- 12. Heterogeneous System-Level Cosimulation with SDL and Matlab -- 13. VHDL-Based HW/SW Cosimulation of Microsystems -- 14. Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling -- 15. A Comparison of Six Languages for System Level Description of Telecom Applications -- 16. High Level Modelling in SDL and VHDL+ -- 17. ECL: A Specification Environment for System-Level Design -- 18. The MCSE Approach for System-Level Design -- Synthesis -- 19. Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement -- 20. VHDL Dynamic Loop Synthesis -- 21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System -- Formal Verification -- 22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation -- 23. Formal Verification of VHDL using VHDL-Like ACL2 Models -- 24. Specification of Embedded Monitors for Property Checking -- 25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL
Dimensions
unknown
Extent
1 online resource (ix, 306 p.)
File format
unknown
Form of item
online
Isbn
9781475733266
Isbn Type
(electronic bk.)
Level of compression
uncompressed
Other control number
10.1007/978-1-4757-3326-6
Quality assurance targets
unknown
Reformatting quality
access
Sound
unknown sound
Specific material designation
remote
System control number
  • (OCoLC)851830646
  • (OCoLC)ocn851830646
Label
Electronic Chips & Systems Design Languages, edited by Jean Mermet, (electronic resource)
Link
http://dx.doi.org/10.1007/978-1-4757-3326-6
Publication
Antecedent source
file reproduced from original
Color
mixed
Contents
VHDL Extensions -- 1. Library Development Using the VHDL-AMS Language -- 2. Behavioral Modeling of Complex Heterogeneous Microsystems -- 3. VHDL-AMS, a Unified Language to Describe Multi-Domain, Mixed-Signal Designs. Mechatronic Applications -- 4. Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique -- 5. SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling -- 6. Digital Circuit Design with Objective VHDL -- System Level Design -- 7. UF: Architecture and Semantics for System-Level Multiformalism Descriptions -- 8. Automatic Interface Generation among VHDL Processes in HW/SW Co-Design -- 9. System-Level Specification and Architecture Exploration: An Avionics Codesign Application -- 10. Using SDL to Model Reactive Embedded System in a Co-design Environment -- 11. A Synchronous Object-Oriented Design Flow for Embedded Applications -- 12. Heterogeneous System-Level Cosimulation with SDL and Matlab -- 13. VHDL-Based HW/SW Cosimulation of Microsystems -- 14. Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling -- 15. A Comparison of Six Languages for System Level Description of Telecom Applications -- 16. High Level Modelling in SDL and VHDL+ -- 17. ECL: A Specification Environment for System-Level Design -- 18. The MCSE Approach for System-Level Design -- Synthesis -- 19. Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement -- 20. VHDL Dynamic Loop Synthesis -- 21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System -- Formal Verification -- 22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation -- 23. Formal Verification of VHDL using VHDL-Like ACL2 Models -- 24. Specification of Embedded Monitors for Property Checking -- 25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL
Dimensions
unknown
Extent
1 online resource (ix, 306 p.)
File format
unknown
Form of item
online
Isbn
9781475733266
Isbn Type
(electronic bk.)
Level of compression
uncompressed
Other control number
10.1007/978-1-4757-3326-6
Quality assurance targets
unknown
Reformatting quality
access
Sound
unknown sound
Specific material designation
remote
System control number
  • (OCoLC)851830646
  • (OCoLC)ocn851830646

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