The Resource CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test, by Andrei Pavlov, Manoj Sachdev, (electronic resource)

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test, by Andrei Pavlov, Manoj Sachdev, (electronic resource)

Label
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test
Title
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Title remainder
Process-Aware SRAM Design and Test
Statement of responsibility
by Andrei Pavlov, Manoj Sachdev
Creator
Contributor
Author
Author
Subject
Language
  • eng
  • eng
Summary
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies
Member of
Is Subseries of
http://library.link/vocab/creatorName
Pavlov, Andrei
Dewey number
621.38152
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsaut
  • lIzbLYj3UZc
  • m4o4nlt_6aA
Language note
English
LC call number
TK7888.4
Literary form
non fiction
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
Sachdev, Manoj.
Series statement
Frontiers in Electronic Testing,
Series volume
40
http://library.link/vocab/subjectName
  • Systems engineering
  • Memory management (Computer science)
  • Circuits and Systems
  • Memory Structures
Label
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test, by Andrei Pavlov, Manoj Sachdev, (electronic resource)
Instantiates
Publication
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques
Dimensions
unknown
Edition
1st ed. 2008.
Extent
1 online resource (205 p.)
Form of item
online
Isbn
9781281492234
Media category
computer
Media type code
c
Other control number
10.1007/978-1-4020-8363-1
Specific material designation
remote
System control number
  • (CKB)1000000000440642
  • (EBL)371551
  • (OCoLC)272298680
  • (SSID)ssj0000123959
  • (PQKBManifestationID)11134080
  • (PQKBTitleCode)TC0000123959
  • (PQKBWorkID)10016316
  • (PQKB)11417104
  • (DE-He213)978-1-4020-8363-1
  • (MiAaPQ)EBC371551
  • (EXLCZ)991000000000440642
Label
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test, by Andrei Pavlov, Manoj Sachdev, (electronic resource)
Publication
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques
Dimensions
unknown
Edition
1st ed. 2008.
Extent
1 online resource (205 p.)
Form of item
online
Isbn
9781281492234
Media category
computer
Media type code
c
Other control number
10.1007/978-1-4020-8363-1
Specific material designation
remote
System control number
  • (CKB)1000000000440642
  • (EBL)371551
  • (OCoLC)272298680
  • (SSID)ssj0000123959
  • (PQKBManifestationID)11134080
  • (PQKBTitleCode)TC0000123959
  • (PQKBWorkID)10016316
  • (PQKB)11417104
  • (DE-He213)978-1-4020-8363-1
  • (MiAaPQ)EBC371551
  • (EXLCZ)991000000000440642

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