The Resource Architecture-Independent Loop Parallelisation, by Radu C. Calinescu, (electronic resource)

Architecture-Independent Loop Parallelisation, by Radu C. Calinescu, (electronic resource)

Label
Architecture-Independent Loop Parallelisation
Title
Architecture-Independent Loop Parallelisation
Statement of responsibility
by Radu C. Calinescu
Creator
Author
Author
Subject
Language
  • eng
  • eng
Summary
Architecture-independent programming and automatic parallelisation have long been regarded as two different means of alleviating the prohibitive costs of parallel software development. Building on recent advances in both areas, Architecture-Independent Loop Parallelisation proposes a unified approach to the parallelisation of scientific computing code. This novel approach is based on the bulk-synchronous parallel model of computation, and succeeds in automatically generating parallel code that is architecture-independent, scalable, and of analytically predictable performance
Member of
http://library.link/vocab/creatorName
Calinescu, Radu C
Dewey number
004.1
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsaut
o9f9m-lBFL4
Image bit depth
0
Language note
English
LC call number
TK7895.M5
Literary form
non fiction
Nature of contents
dictionaries
Series statement
Distinguished Dissertations
http://library.link/vocab/subjectName
  • Computer science
  • Software engineering
  • Processor Architectures
  • Special Purpose and Application-Based Systems
  • Programming Techniques
Label
Architecture-Independent Loop Parallelisation, by Radu C. Calinescu, (electronic resource)
Instantiates
Publication
Note
Bibliographic Level Mode of Issuance: Monograph
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Color
not applicable
Content category
text
Content type code
  • txt
Contents
1 Introduction -- 1.1 Motivation -- 1.2 Parallelisation Approach Proposed in the Book -- 1.3 Organisation of the Book -- 2 The Bulk-Synchronous Parallel Model -- 2.1 Introduction -- 2.2 Bulk-Synchronous Parallel Computers -- 2.3 The BSP Programming Model -- 2.4 The BSP Cost Model -- 2.5 Assessing the Efficiency of BSP Code -- 2.6 The Development of BSP Applications -- 2.7 BSP Pseudocode -- 3 Data Dependence Analysis and Code Transformation -- 3.1 Introduction -- 3.2 Data Dependence -- 3.3 Code Transformation Techniques -- 4 Communication Overheads in Loop Nest Scheduling -- 4.1 Introduction -- 4.2 Related Work -- 4.3 Communication Overheads Due to Input Data -- 4.4 Inter-Tile Communication Overheads -- 4.5 Summary -- 5 Template-Matching Parallelisation -- 5.1 Introduction -- 5.2 Related Work -- 5.3 Communication-Free Scheduling -- 5.4 Wavefront Block Scheduling -- 5.5 Iterative Scheduling -- 5.6 Reduction Scheduling -- 5.7 Recurrence Scheduling -- 5.8 Scheduling Broadcast Loop Nests -- 5.9 Summary -- 6 Generic Loop Nest Parallelisation -- 6.1 Introduction -- 6.2 Related Work -- 6.3 Data Dependence Analysis -- 6.4 Potential Parallelism Identification -- 6.5 Data and Computation Partitioning -- 6.6 Communication and Synchronisation Generation -- 6.7 Performance Analysis -- 6.8 Summary -- 7 A Strategy and a Tool for Architecture-Independent Loop Parallelisation -- 7.1 Introduction -- 7.2 Related Work -- 7.3 A Two-Phase Strategy for Loop Nest Parallelisation -- 7.4 BSPscheduler: an Architecture-Independent Loop Paralleliser -- 7.5 Summary -- 8 The Effectiveness of Architecture-Independent Loop Parallelisation -- 8.1 Introduction -- 8.2 Matrix-Vector and Matrix-Matrix Multiplication -- 8.3 LU Decomposition -- 8.4 Algebraic Path Problem -- 8.5 Finite Difference Iteration on a Cartesian Grid -- 8.6 Merging -- 8.7 Summary -- 9 Conclusions -- 9.1 Summary of Contributions and Concluding Remarks -- 9.2 Future work directions
Dimensions
unknown
Edition
1st ed. 2000.
Extent
1 online resource (XVIII, 172 p.)
File format
multiple file formats
Form of item
online
Isbn
9781447107637
Level of compression
uncompressed
Media category
computer
Media type code
  • c
Other control number
10.1007/978-1-4471-0763-7
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (CKB)3400000000088298
  • (SSID)ssj0000933596
  • (PQKBManifestationID)11589827
  • (PQKBTitleCode)TC0000933596
  • (PQKBWorkID)10891445
  • (PQKB)11199409
  • (DE-He213)978-1-4471-0763-7
  • (MiAaPQ)EBC3074124
  • (EXLCZ)993400000000088298
Label
Architecture-Independent Loop Parallelisation, by Radu C. Calinescu, (electronic resource)
Publication
Note
Bibliographic Level Mode of Issuance: Monograph
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Color
not applicable
Content category
text
Content type code
  • txt
Contents
1 Introduction -- 1.1 Motivation -- 1.2 Parallelisation Approach Proposed in the Book -- 1.3 Organisation of the Book -- 2 The Bulk-Synchronous Parallel Model -- 2.1 Introduction -- 2.2 Bulk-Synchronous Parallel Computers -- 2.3 The BSP Programming Model -- 2.4 The BSP Cost Model -- 2.5 Assessing the Efficiency of BSP Code -- 2.6 The Development of BSP Applications -- 2.7 BSP Pseudocode -- 3 Data Dependence Analysis and Code Transformation -- 3.1 Introduction -- 3.2 Data Dependence -- 3.3 Code Transformation Techniques -- 4 Communication Overheads in Loop Nest Scheduling -- 4.1 Introduction -- 4.2 Related Work -- 4.3 Communication Overheads Due to Input Data -- 4.4 Inter-Tile Communication Overheads -- 4.5 Summary -- 5 Template-Matching Parallelisation -- 5.1 Introduction -- 5.2 Related Work -- 5.3 Communication-Free Scheduling -- 5.4 Wavefront Block Scheduling -- 5.5 Iterative Scheduling -- 5.6 Reduction Scheduling -- 5.7 Recurrence Scheduling -- 5.8 Scheduling Broadcast Loop Nests -- 5.9 Summary -- 6 Generic Loop Nest Parallelisation -- 6.1 Introduction -- 6.2 Related Work -- 6.3 Data Dependence Analysis -- 6.4 Potential Parallelism Identification -- 6.5 Data and Computation Partitioning -- 6.6 Communication and Synchronisation Generation -- 6.7 Performance Analysis -- 6.8 Summary -- 7 A Strategy and a Tool for Architecture-Independent Loop Parallelisation -- 7.1 Introduction -- 7.2 Related Work -- 7.3 A Two-Phase Strategy for Loop Nest Parallelisation -- 7.4 BSPscheduler: an Architecture-Independent Loop Paralleliser -- 7.5 Summary -- 8 The Effectiveness of Architecture-Independent Loop Parallelisation -- 8.1 Introduction -- 8.2 Matrix-Vector and Matrix-Matrix Multiplication -- 8.3 LU Decomposition -- 8.4 Algebraic Path Problem -- 8.5 Finite Difference Iteration on a Cartesian Grid -- 8.6 Merging -- 8.7 Summary -- 9 Conclusions -- 9.1 Summary of Contributions and Concluding Remarks -- 9.2 Future work directions
Dimensions
unknown
Edition
1st ed. 2000.
Extent
1 online resource (XVIII, 172 p.)
File format
multiple file formats
Form of item
online
Isbn
9781447107637
Level of compression
uncompressed
Media category
computer
Media type code
  • c
Other control number
10.1007/978-1-4471-0763-7
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (CKB)3400000000088298
  • (SSID)ssj0000933596
  • (PQKBManifestationID)11589827
  • (PQKBTitleCode)TC0000933596
  • (PQKBWorkID)10891445
  • (PQKB)11199409
  • (DE-He213)978-1-4471-0763-7
  • (MiAaPQ)EBC3074124
  • (EXLCZ)993400000000088298

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